The present invention generally relates to a semiconductor memory device having redundant memory cells, and more particularly to an improvement in reading of data from a memory cell array.
Recently, it has been required to increase the storage capacity of semiconductor memory devices. For this requirement, a huge number of memory cells are arranged in an IC chip. The number of defective memory cells increase when there is a reduction in the size of each memory cell. In order to cope with this problem, a predetermined number of redundant memory cells are arranged in the memory cell array. On the other hand, it is required to increase the operation speed of the device together with a reduction in the size of memory cells. For this requirement, an address transition detector is employed.
Referring to FIG. 1A, there is illustrated a conventional semiconductor memory device (an erasable programmable read only memory device), which has redundant memory cells and the address transition detector. An input address signal A generated and output by an external device, such as a central processing unit, is input to an address buffer 1. The address buffer 1 generates an address buffer output signal B corresponding to the input address signal A, and sends the same to a decoder 2, an address transition detection pulse generator (hereinafter simply referred to an ATD pulse generator) 6 and a redundancy circuit 7.
The decoder 2 decodes the address buffer output signal B and outputs a decode output signal C to a memory cell array 3. The decode output signal C specifies one word line and one bit line provided in the memory cell array 3. Thereby, a memory cell coupled to the selected word line and the selected bit line is selected.
On the other hand, the ATD pulse generator 6 detects an address transition from the address buffer output signal B and generates, therefrom, an ATD pulse signal D having a predetermined pulse duration time t.sub.1 (hereinafter also referred to as a reset time). The ATD pulse signal D is sent to the memory cell array 3, a sense amplifier 4 and a data output buffer 5. During the reset time t.sub.1, the bit lines in the memory cell array 3, the sense amplifier 4 and the data output buffer 5 are reset so that the device is set in a data read enable state. For example, during the reset time, the bit lines in the memory cell array 3 are precharged to a predetermined precharge voltage (approximately 1 volt, for example). The sense amplifier 4 has a differential amplifier having two input terminals coupled to a pair of bit lines. During resetting, two input terminals are short-circuited (equalized) so that they become equal to an identical potential. Output transistors in the data output buffer 5 are set to a high-impedance state during the reset time.
Addresses of defective memory cells are stored in a defective address memory 8. The addresses of defective memory cells are obtained by a predetermined test. The redundancy circuit 7 compares the input address signal A with the addresses of the defective memory cells, and determines whether or not the input address signal A indicates one of the defective memory cells. When it is determined that the input address signal A indicates one of the defective memory cells, the redundancy circuit 7 outputs a redundancy signal E to the decoder 2. In response to the redundancy signal E, the decoder 2 decodes the address buffer output signal B again and outputs the decode output signal C which specifies a corresponding spare (redundant) memory cell provided in the memory cell array 3. In this way, the accessed defective memory cell is replaced by the specified spare memory cell.
FIG. 1B shows a detailed configuration of the memory cell array 3. As shown, the memory cell array 3 is composed of memory cells MC coupled to bit lines and word lines, and redundant memory cells RMC coupled to bit lines and word lines. The memory cells MC contain defective memory cells.
However, the semiconductor memory device shown in FIG. 1 has the following disadvantages, which will be explained below with reference to FIG. 2. An address transition occurs at time t.sub.0 (FIG. 2-(a)). At this time, the ATD pulse signal D is generated by the ATD pulse generator 6 (FIG. 2-(b)). The ATD pulse D has a high level during the time t.sub.1. As has been described previously, during the time t.sub.1, the memory cell array 3, the sense amplifier 4 and the data output buffer 5 are reset. As shown in FIG. 2-(c), due to the comparison operation in the redundancy circuit 7, the redundancy signal E rises with a delay time t.sub.2 from the address transition time t.sub.0. That is, the rise of the redundancy signal E lags behind that of the ATD pulse signal by time t.sub.2. As a result, in actuality, the reset time is reduced by time t.sub.2 so that it becomes equal to t.sub.3 (=t.sub.1 -t.sub.2) In this case, there is a possibility that the memory cell array 3, the sense amplifier 4 and the data output buffers will not be completely reset when the time t.sub.1 elapses. For example, the bit lines in the memory cell array 3 are not completely precharged during the reduced reset time. The sense amplifier 4 is not completely equalized. In other words, data is read out before the specified redundant memory cell is completely selected. If data is read out from the memory cell array 3 immediately after the elapse of the time t.sub.1, there is a high possibility of an error being contained in the readout data.